Conventional approaches for performing flip chip stacking involve placing a through-silicon-via (TSV) interposer on an organic substrate and subsequently stacking an integrated circuit on the TSV interposer to form a flip chip. Such conventional methods for flip chip stacking are characterized by the particular bonding methods and process parameters involved. Assembly yield for flip chip stacking is significantly influenced by TSV interposer warpage that occurs during conventional flip chip stacking. Conventional flip chip stacking approaches lead to significant amounts of TSV interposer warpage that ultimately affects IC performance and assembly yield.
One approach currently being studied for mitigating the effects of TSV interposer warpage is thermo-compression bonding of IC dies to TSV interposers. However, thermo-compression bonding leads to several side effects such as flux residue and uneven heat profiles, which in turn result in poor soldering performance.